Force Technologies FPGA to Structured ASIC, Hybrid or Standard Cell conversions.
Force can take your existing Gate Array, CPLD, EPLD, FPGA product, and redesign to an ASIC, respin the printed circuit board, and provide a complete manufacturing package for a replacement product, all with minimal impact on other projects. Force can supply IP for multiple obsolete components, and implement them in a single device, achieving cost and power savings. Devices can be manufactured and screened to Industrial -40oC to +85oC standards SnPb or Pb free.

Synthesis IP of standard devices and buses for use as elements in the design of FPGAs and ASICs. Some of the IP components have a variety of features that can be enabled and configured at synthesis. Features disabled during synthesis are excluded from the target netlist providing an efficient core that can be configured into many different components without gate count overhead. All cores are shipped in source format and without multi-use licensing fees.

 FPGA to ASIC Conversion Presentation

Family	Application	Description	Graphic
Standard Cell	Standard EDA software Economic Efficient	Force's Standard Cell ASICs, which use a full set of masks for fabrication, are the approach of choice for very high volume, stable designs as well as highly complex designs requiring ultimate performance. Once a design has been proven in the market and has predictable production volumes, Standard Cell ASICs deliver the best efficiency and economy. Based on the customer's design, the required circuits are placed on the chip and connected using industry standard EDA software. Standard Cell ASICs can integrate mixed-signal IP elements from Force or third parties to create a System-on-Chip (SoC) device.  Unlike Structured ASICs, Embedded Arrays or Gate Arrays, which start with partially fabricated wafers of repetitive blocks of unconnected standard elements, Standard Cell designs are created on blank wafers. The design therefore only includes the exact requirements of the application, leading to more efficient use of silicon area.  The designer can adjust the number of routing layers to reach timing closure and balance die size with the number of metal layers used.
Structured ASIC	Low NRE Fast turnround Simple Reconfiguration	Structured ASICs, also known as Platform ASICs, are an enhanced form of Gate Arrays that were invented in the early 1980s.  Structured ASICs remove the complexity of custom silicon design by providing a fabric of configurable logic cell building blocks (or Structured Array), the Chip, combined with easily configurable memory and I/O structures. Using only industry standard design automation tools, the logic portion of the design is configured on the Structured ASIC fabric (or array) using the top layers of metal, enabling the lower layers to be pre-built and used by multiple customer designs. Certain Structured ASIC families also include pre-validated mixed-signal IP, which reduces the risk of integration significantly as well as the development time.  Our Structured ASICs offer the additional benefit of simple re-configuration, allowing very rapid design changes using industry standard routing and layout tools eliminating the need for tedious and often risky manual rework or Engineering Change Orders (ECO). Embedded Arrays are Gate Arrays that integrate fixed compiled memory. Unlike Structured ASICs, re-spins that entail a different memory configuration require an all layer change.
Hybrid ASIC	Small die Upgrade able	Hybrid ASICs are Standard Cell ASICs with an embedded IP core of configurable logic or Structured Array.  This approach provides the smallest die size possible, while providing some flexibility for re-configuration of certain functions using metal layers only.  The configurable logic core can be customised to be any size or shape.  The designer decides what function, or portion of the design, will be implemented in the configurable logic core.  The designer may decide to save that space empty for future feature enhancements, saving time and cost of developing derivative products.  Ideal applications for a Hybrid ASIC include encryption engines, compression algorithms, interface protocols and pre-standard implementations of a new or evolving standard.

 TYPICAL EMULATIONS and exact FPGA conversions