The Current State of the Art for Managing Electronic Component Obsolescence

Why Obsolescence Management?

Modern electronic equipment can have a production life including spare part requirements of up to 30 years. However the components that are used to build the product will have a production life much shorter than that. This creates significant problems for the equipment manufacturer who needs to mitigate against the following risks:

  • from a different manufacturer
  • ‘last time buys’ (LTB) or ‘Die Banking’. Buying the components in bulk and store them in inventory for future needs. The life cycle of the end product is reduced
  • The production cost of the end product can rise
  • The end product becomes impossible to support and service
  • The end product must be redesigned
  • The redesigned end product must be re-qualified and certified

Effective obsolescence management help avoid the costs and risks associated with redesigning the end product. It is essential to find a reliable partner with a long history of obsolescence management. The necessary skills and contacts take many years to develop. Once a part goes EOL you have the following broad range of options:

  • Finding Form, Fit and Function replacements
  • Finding nearest equivalent alternate part, to reduce the redesign cost.
  • Recreating the EOL component
  • Redesign and requalify a sub-section or the entire equipment

This white paper outlines the various options available to ensure continuing availability of electronic components and to avoid the need for product redesign and recertification.

FPGA Remanufacturing and Emulation

Method: Replace old FPGA or other discrete parts with a modern lead free FPGA

Useage: When the original part is now longer available and can be recreated in logic

The efficiency of modern FPGA solutions makes them very attractive to system engineers facing component obsolescence issues.

One of the key reasons to retarget a legacy silicon solution to a modern FPGA is to achieve better quality of results (QoR)–namely, increased throughput speed. The current mainstream process technology–130 nm–will provide high-performance solutions with internal frequencies of up to 200 MHz. Within a 90-nm device, 500-MHz internal frequencies are possible.

Modern FPGAs are often ideal replacements for end-of-life FPGAs, CPLDs, and ASSPs like PCI controllers and physical-layer interfaces. A single-chip FPGA solution on the printed-circuit board is attractive, as it eliminates the need for an additional configuration device. Another issue is the European Union’s Restriction of Hazardous Substances (RoHS) directive, which is forcing system engineers to adopt modern lead-free devices.

It can be expensive to maintain and replace legacy devices with the same-generation process technology as the original. Low-cost FPGA devices, which are designed specifically to address higher volume product applications, are often a superior alternative.

Reverse Engineering

Method: Re Creating Semiconductors from a single sample

Useage: When some original parts are available but the original designs are not

Reverse engineering of integrated circuits involves examining a chip to see how it operates and recreating the original design documentation to allow it to be remanufactured.

The first step in reverse engineering an integrated circuit is to remove the silicon (or other semiconductor) die from the plastic or metal chip carrier in a process called die extraction.

The bare die is examined under an electron microscope to identify the circuit elements and how they are interconnected. This is done by taking a high resolution image of each layer of the chip (subsequent layers are exposed in a process called de-processing). Once the three dimensional image is compiled, software is employed that extracts the circuit elements and the net list (interconnection wiring).

Software and firmware can be disassembled to observe how it functions. Sometimes the operation of a microprocessor or a PLD/FPGA can be determined solely by observing the inputs and outputs, often the machine code itself must be evaluated.

The results, usually a block diagram, schematic diagram, circuit board layout, flowchart, netlist table, raw program code and operational documentation are now verified and made available for re manufacturing.

Die Recovery and Repackaging

Method: Extract existing die, repackage and test

Useage: When the original die is only available in a non suitable package

In many cases, due to component obsolescence, the required device package configuration in the original build of materials (e.g., DIP, SOIC, LCC, PQFP, etc., or possibly even bare die cannot be located despite the correct silicon die revision which is readily available in an alternate package footprint(s).

There are now cost-effective, high-volume extraction techniques to remove silicon die from any plastic package and re-assemble them into any other plastic or Hermetic Ceramic JEDEC, metal can or custom package.

The die extraction process relies on chemical and mechanical processes that are no more aggressive than those when the original die as exposed during device manufacture.

Once the die has been successfully harvested, the original gold wires are mechanically removed just above the original gold ball bond, providing a clean, uncontaminated gold surface for high adhesion re-bonding.

The only subsequent non-standard assembly process is that a new gold ball bond is made to the existing gold ball bond surface, rather than to the original aluminium pad interface. Under proper process optimisation, the new gold bond on the existing gold ball bond adheres extremely well with pre and post die extraction/re-assembly bond pull data which is not only indistinguishable in both cases, but also generally limited to the tensile strength of the bond wire used.

Additional test data referencing die shear and bond shear is also statistically identical for pre and post extraction/reassembly processing. Lastly, the extraction and re-assembly processing can be shown to have the added benefit of providing inspected, genuine silicon for subsequent re-assembly, while significantly reducing the possibility of inadvertent use of counterfeit devices in military systems.

Many MCM manufactures can now use harvested devices from COTS to prepare prototypes before committing to wafer quantities.


Method: Test existing finished product and select those which meet higher spec

Useage: When commercial parts are available that may meet a higher spec


When specialist grade semiconductors come to their end of life become obsolete, a variant may be commercially available. Upscreening commercial or Industrial parts to a higher specification or indeed screening a military temperature grade part to Mil-Std-883 M5004 offers a viable, cost effective and sustainable solution to the problem.

Up screening follows a process of evaluation that requires highly skilled engineering;

Having identified and sourced a viable and readily available variant component in ceramic, metal Can or plastic package. The devices undergo a wide range of electrical and environmental tests (including Burn in and Environmental tests) to establish quality and long-term reliability. Military grade tests include MIL-STD-883 M5004

Device Characterisation

Device characterisation helps to meet ever-more stringent demands for device reliability.

Characterisation of ICs begins with serialised electronic testing to identify operational characteristics. These are compared with existing Gold Standard parameters detailed in OEM documentation. Once batch test results are within specific characteristics, the process of device characterisation is complete; the process can then move onto production test or report

DPA (Destructive Physical Analysis)

DPA sample testing is performed to exacting specifications, ensuring high reliability of components and devices that are fabricated to a required standard.

Analysis collects data to help determine any items that may function out of original spec thus preventing rejection of entire lots. Screening identifies:

  • Exact construction
  • Composition
  • Quality of materials/components contained

Typical DPA can include:

  • External, visual inspection – to assess overall exterior quality and workmanship.
  • Real Time X-Ray Inspection – non-destructive detection of internal defects
  • Particle Impact Noise Detection – to detect loose particles inside a device cavity.
  • Hermetic and Internal Vapour Analysis – to quantify package integrity & internal
    atmosphere; methods may be used to gauge sealing processes or internal post-seal out
    gassing to prevent susceptibility to moisture-related failures.
  • Internal Visual Inspection via Optical Microscopy and Scanning Electron Microscopy
    (SEM) – to evaluate the quality of passivation, metallisation and other die related components.
  • Glassivation Layer Integrity – to assess the structural quality of deposited dielectric films
    over aluminium metallised devices.
  • Bond Strength – to measure wire bond strengths and evaluate bond strength


Plastic Encapsulated Microcircuits (PEMs) are becoming widely accepted in Avionics, Telecommunications, Military and Space applications due to the advantages offered in size, weight, cost and availability.

The mil-plastic test screening, Relplas, available from Force Technologies Ltd via its approved Vendors, upgrades commercial and industrial grade products with extended testing to qualify for military applications.

Relplas™ offers lower cost, low-weight options for COTS ICs with improved specifications over the standard of equivalent components.

Anti Counterfeit Testing

Method: Test parts visually, mechanically and electronically to ensure originality

Usage: When provenance cannot be guaranteed

Counterfeits are becoming harder to detect; scrap Die is used to pass x-ray tests, whilst packaging and marking often passes initial examination.

The Aerospace AS5553 Standard, Counterfeit Electronic Parts; Avoidance, Detection, Mitigation, and Disposition, was developed by the G-19 committee of SAE International. It is important to verify parts of unknown provenance in accordance with this specification.

The standard is designed for adoption by aerospace and military manufacturers and contractors, providing uniform requirements, practices and methods to mitigate the risk of receiving and installing counterfeit electronic parts. The AS5553 standard documents requirements, practices and methods related to:

  • Parts management
  • Supplier management
  • Procurement
  • Inspection, test/evaluation, and response strategies when suspect parts are discovered.

Technical tests that may be carried out on suspect parts include:

  • DDI (Device Die Identification) – prevents counterfeiters from changing wafer masks,
    identifiable as OEM.
  • CPI (Critical Parametric Identification) – ensuring variants are unique to the actual device specification.
  • DMV (Die Metallurgical Verification) – Scanning using an electron microscope to determine composite materials.

Die Banking

Method: Store bare die bought at Last time buy. Package for production as required

Usage: When bare die are offered as a last time buy this is secure and cost effective method of

Die banking is a cost effective method of taking advantage of last time buys and offers cost effective long term security for a project which otherwise may need a complete re-design.

Following a last time buy against forecast product requirements bare die are stored until they are needed. The cost of bare die being less than the packaged product there are financial as well as reliability benefits of storing in this way

Bare die are particularly sensitive, and need to be stored in meticulously controlled conditions. Due to their metal composition, bare die need to be excluded from contact with air to prevent oxidization on the die. Also die need to be carefully protected from ESD as without taking the proper precautions the electrical quality of the product can deteriorate over time.

The expertise needed to monitor storage conditions and pick the appropriate carrier for the product is developed over a long period of time

Maintaining precise traceability is vital to die banking, product needs to be quickly identified and prepared for shipment when required.

Re-creation Using Existing Die

Method: Purchase bare die, repackage and test

Useage: When the original die is available unpackaged or can be remanufactured

This solution simply re-creates of EOL (end of life) or obsolete semiconductor and items that demand an extended life-cycle forecast; all to original manufacturer’s design specifications or equivalent.

A vast range of packaged die options are available. Bare die or wafer are lot qualified or can be probed over temperature and meet MIL-STD-883 standards. Die & wafers can be reengineered and re-manufactured to original package designs or to cater for specific requirements lead-free or green standards

Mechanical Re-Working

Method: Convert to lead free, Laser Mark, Realign and repackage

Useage: Prepare recovered or storage damaged parts for production use

Reworking or modifying components to meet the original or specific, new mechanical specification is a cost-effective way of managing the availability of obsolete semiconductors and electronic components

There are a number of standard and custom mechanical methods available to re-work existing damaged components


Reballing allows the manufacturer to re-use parts as well as convert them from tin-lead (Sn63Pb37 or Sn10Pb90) to lead-free

Lead Alignment

Quad Flat Pack (QFP), DIL and Small Outline Integrated Circuit (SOIC) component lead alignment of physically damaged parts is essential for reliable and cost effective machine placement.

Taping and Reeling

Taping & reeling of mechanically recovered parts to EIA standards including testing for peel strength allow their re-use in automatic placement systems

Laser Marking

Laser marking ensures clear identification and effective quality control.