Xilinx XC4000 series FPGA
Xilinx XC4000 series FPGA

Force Technologies offer a number of solutions to Xilinx FPGA obsolescence and counterfeit prevention.

  1. Adapt device using a “transposer” board with or without VCC conversion.
  2. Adapt device by upscreening to a higher specification by test methods including adapting to Pb or RoHS requirements.
  3. ADR (Advanced Die reclamation) – harvesting Xilinx die from unsuitable packaging and replacing with suitable packaging.
  4. Converting Xilinx FPGA by creating a FFF ASIC.
  5. FPGA substitution and emulation

Solutions for Xilinx Semiconductors

Transposer Board

A transposer board consists of a suitable multi layer material (FR or ceramic) with suitable connections on the surface for the available Xilinx current device and correct connections on the underside for the unavailable Xilinx device pinned out to suit the PCB in use.


By using a lower grade being a suitable and available device we can subject it to rigorous high grade assembly and test with recommendations for high yield and reliability upscreening from Commercial to Industrial grade, or industrial to Military grade.

Advanced Die Reclamation

Using ADR on high count pin devices allows us to remove Xilinx die cleanly and with no harm or degradation from plastic or ceramic available packages. This allows us to repackage the die into the correct part. This also allows us to use larger cell parts to be down pinned to smaller cell parts being FFF as the original.

FPGA to ASIC Conversion

Xilinx FPGA can be converted by creating a pin-for-pin migration to a FFF structured ASIC. Force Technologies have been migrating Xilinx and other OEM FPGAs for over a decade. Customers benefit from risk mitigation by liaising designs from RTL or FPGA Netlist.

FPGA Emulation

We are able to reproduce the original part by substituting the FPGA of another manufacturer and using available emulation software.

Scope of Testing

Xilinx user-programmable gate arrays include 3 major configurable elements.

  1. Configurable logic blocks (CLBs)
  2. CLBs provide the functional elements for constructing the user’s logic
  3. Input/output blocks (IOBs)
  4. IOBs provide the interface between the package pins and internal signal lines
  5. Interconnect (Long Lines)
  6. Programmable Interconnect resources provide routing paths to connect the inputs and outputs of these configurable elements to the appropriate networks.
  7. Functional Patterns designed to verify correct operation of all the IOBs and CLBs


  • First designs targeting the various architectures are created with Xilinx Foundation ISE software package to encompass the Scope of Testing. These are unconventional designs created to target the worse case timing delays for the device’s architecture.
  • Bit streams used to configure the device to be tested are generated.
  • Test Limits for are generated based on speed grade and temperature rating of the requested device (Up screening or Verification).
  • Devices are then programmed using PC and Xilinx programming hardware.
  • Devices are tested at Room Temperature, Specified Hot, and Cold (if requested). Tested to specified temperature rating for C, I, or M grade ranges.
  • Signal generator and logic analyzer are used to take measurements using specified signal and supply level.
  • Measurements are then compared to test limits and results are published.

Parameters Tested

DC Testing (Direct):

  • VCC
  • ICCO
  • VIH
  • VIL
  • VOH

Test Pattern Measurements (Indirect):

  • Global Buffer Switching Characteristics
    • TPG
  • Horizontal Longline Switching Characteristics
    • TIO1
  • CLB Switching Characteristics
    • TILO
    • TIHO
    • TCKO
  • IOB Input Switching Characteristics
    • TPID
    • TOPF

Source Control Drawing for FT800-QM6115 – a military obsolescence alternative to Xilinx XC4010 device.

Case Sudy on XC3000 series device, obsolesce solution.

Xilinx Recreation